1. Field of the Invention
The invention relates to a method for manufacturing a semiconductor device and a NAND-type flash memory having element isolation regions.
2. Related Art
In order to miniaturize a semiconductor device, it is important to miniaturize element isolation regions for insulating elements from each other. As one of element isolation techniques, an STI (Shallow Trench Isolation) technique is used to fill minute trenches formed in a semiconductor substrate with an insulating film. In order to miniaturize the semiconductor device, it is necessary to narrow the width of STI trenches, and the trenches can have a width of 30 nm or smaller in recent years. As the width of the trench becomes smaller, the ratio of the trench depth to the trench width (aspect ratio) becomes relatively large. This is because the trench having the small aspect ratio decreases insulation property.
For example, it is inevitable for miniaturizing a NAND-type flash memory to narrow the trench width between memory cells for storing 1-bit information, and thus aspect ratio of the trench has to be enlarged. On the other hand, the width of the element isolation region arranged between a memory cell and a peripheral circuit such as a control circuit may be relatively large, which leads to a small aspect ratio, and particularly high insulation property is required in order to decrease leak current.
Generally, insulating films for isolating elements are formed by a high density plasma CVD (Chemical Vapor Deposition) technique, for example. Because the high density plasma CVD technique can form high quality insulating films having high insulation property. However, it is difficult to form the insulating film in the STI trench having a large aspect ratio by the high density plasma CVD technique. This is because, in this technique, step coverage (the ratio of the film thickness in the trench portion to that in the flat portion) is poor and the opening of a trench having a high aspect ratio is stuffed before completely filling the trench itself.
In another technique, the insulating film can be formed by filling the trench with a coating material and oxidizing the coating material. However, there is a problem that the bottom of the trench having a large aspect ratio cannot be sufficiently oxidized, thereby worsening the insulation property. In addition, the insulating film formed of the coating material contains more impurities than that formed by the high density plasma CVD technique. Therefore it is difficult to secure the insulation property required for element isolation between the memory cell and the peripheral circuit.
Patent document 1 (JP-A No. 2003-31650 (Kokai)) discloses a technique in which the bottom of the trench is filled with a high quality SiO2 film by the high density plasma CVD technique while the top of the trench is filled with SiO2 of a coating material. However, as stated above, it is difficult to fill the trench having a large aspect ratio with SiO2 by the high density plasma CVD technique.